TRW Space and electronics group

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2001 contract - Photo of Clock Recovery Module front and rear without covers.  As a contractor, I received this interesting design task to update and repackage their existing clock recovery design into this VXI form factor to support their new ground station receiver product line. The module supported 4 symbol rates, 1600, 800, 400 Msps, with the last slot unused.  The design supported multiple modulation formats with stringent phase noise and Eb/No acquisition requirements. Fortunately I had the assistance of a board layout person along with a mechanical engineer for packaging (D. Kubo, et al). 

RDE for 4-ary Receiver - I was the lead engineer for this design that was used on two separate projects in the mid 1990s. This particular photo is of the 4-ary 4-rate receiver used in a payload test set.  The unit consisted of 5 shielded subassemblies below a fixed deck and two swing planes above to house circuit boards.  Digital carrier recovery was achieve utilizing subsampled demodulated data (D. Kubo, et al).  

2001 - Photo of Divide-by-N board design that provided clock division ratios of 80, 40, 20, and 10. The SMA input connector on the left accepted an analog sinusoid that was converted to ECL for division using logic gates and UT-047 delay lines. The two output connectors on the right provided I & Q staggered clocks to the Track & Hold + ADC board.  The board also provided programmable clock delay to optimize clock to data timing at the TH+ADC board (D. Kubo, et al).  

Track & Hold + ADC board - One of the key elements for the receiver product line was this Track & Hold + ADC board that I developed for the receiver described above.  It accepted a pair of I & Q raw demodulated data at 1600 Msps and subsampled by factor of 80 to a rate of 20 Msps.  The two square openings are where proprietary Tektronix Track & Hold devices dropped in.  The ADCs were commercial Maxim MAX100 100 Msps 8-bit ADCs (D. Kubo, et al).  

Decision Circuit board - Since ADCs capable of capturing data at 1600 Msps were not available at the time, I developed this Decision Circuit board based around an HP high speed ECL D-flip flop. ECL has a nominal input level of -1.3 V (800 mVpp swing) so the Vcc and Vee were offset by 1.3 V to provide 0.0 V input for the analog demodulated data. The output of the D-FF was level shifted back to normal ECL values for distribution by a Line Drive module.  Matched filtering prior to the decision circuit was performed by a 2-pole Butterworth low pass filter, 3 of which are shown on the board to support 3 data rates (D. Kubo, et al)

1998 - I was one of several recipients for the 1998 Chairman's Award for Innovation. This photo is of a much younger me at the TRW headquarters in Cleveland Ohio with then CEO Joe Gorman. They treated us quite well and it was a memorable occasion.   

The innovation was the application of using raw subsampled demodulated data to steer the convergence algorithm of our suite of ground terminal instruments that included a cross polarization canceller and adaptive equalizer.